Model Reduction of Modules for State-Even Temporal Logics

In many Discrete-Event Systems (DES) both state and event information are of importance to the systems designer. Logics such as Ostroff’s RTTL allow for the specification and verification of a system’s state-event behavior. To make realistic problems amenable to analysis, a designer must typically decompose the system into subsystems (modules) and use algebraic abstraction (quotient systems) to obtain hierarchical system models that preserve the properties to be verified. In this paper we use state-event observational equivalence to perform model reduction for a subclass of formulas of state-event linear temporal logics, with particular attention being paid to a discrete time temporal logic that is a simplification of RTTL. The reduction technique allows limited use of immediate operators.